1. Field of Invention
The present invention relates to a switching power supply device for converting a DC voltage to a desired voltage and supplying the same to an electrical apparatus, more particularly relates to technology for synchronized rectification of the same.
2. Description of the Art
A synchronized rectification type switching power supply device is a switching power supply device which uses field effect transistors etc. as rectifiers in place of the usual diodes configuring the rectification circuit and is employed for the purpose of reducing loss by reducing a forward direction voltage drop.
Below, there is described a synchronized rectification type switching power supply device of the art disclosed in Japanese Patent Publication (A) No. 2003-189608 with reference to the attached drawings.
FIGS. 1A to 1F are diagrams for explaining an example of the synchronized rectification type switching power supply device of the art, in which FIG. 1A is a circuit diagram, and FIGS. 1B to 1F are timing charts of portions of it. In the timing charts, FIG. 1B shows an output voltage of a transformer, FIG. 1C shows a gate voltage of an NMOS transistor Q100, FIG. 1D shows the gate voltage of an NMOS transistor Q200, FIG. 1E shows a drain current Id of the NMOS transistor Q100, and FIG. 1F shows a drain current Id of the NMOS transistor Q200.
The switching power supply device shown in FIG. 1A employs the technology of synchronized rectification using current doubler output. In this switching power supply device, when there is no output of the transformer, that is, in a commutation state, energy is released from a filter inductor L10 and the current commutes. At this time, as shown in FIGS. 1C and 1D, the NMOS transistors Q100 and Q200 are turned off. Accordingly, the commutation current is output through parasitic diodes between drains and sources of the NMOS transistors Q100 and Q200. Therefore, a loss at the time of the commutation (commutation loss) is large.
FIGS. 2A to 2F are diagrams for explaining another example of a synchronized rectification type switching power supply device of the art, in which FIG. 2A is a circuit diagram, and FIGS. 2B to 2F are timing charts of different parts. In the timing charts, FIG. 2B shows an output voltage of a transformer, FIG. 2C shows a gate voltage of an NMOS transistor Q100, FIG. 2D shows a gate voltage of an NMOS transistor Q200, FIG. 2E shows a drain current Id of the NMOS transistor Q100, and FIG. 2F shows a drain current Id of the NMOS transistor Q200.
In the switching power supply device shown in FIG. 2A, in comparison with the switching power supply device shown in FIG. 1A, an auxiliary winding, a voltage restriction circuit for restricting gate voltages of the NMOS transistors Q100 and Q200 based on the output signal the auxiliary winding and a discharge circuit are added. Due to this, as shown in FIGS. 2C and 2D, the NMOS transistors Q100 and Q200 are turned on even when there is no output of the transformer, so the above commutation loss is suppressed.
In the switching power supply device shown in FIG. 2A, however, when the input voltage with respect to the transformer widely fluctuates, the voltage restriction circuit is provided for restricting the drive peak voltage to a gate destruction voltage or less, and the drive voltage is clamped to the predetermined restricted value by this. Accordingly, a drive loss of that amount occurs.
Further, at the time of the input of a low voltage, the drive voltage becomes lower than the clamp voltage during the commutation period when there is no transformer output, and the ON resistances of the NMOS transistors Q100 and Q200 increase, therefore the commutation loss increases. For example, a time T5 to T7 of FIG. 2E is the commutation period. At the time T5, the drain current Id of the NMOS transistor Q100 abruptly drops, but in actuality, energy cannot be sharply released from the inductor part, therefore the drain current in the time T5 to T7 remains as a current having a magnitude near the peak current in a time T4 to T5 (see FIG. 9C). On the other hand, as seen in FIG. 2C, in the time T5 to T7 (commutation period), a drive voltage relatively small in comparison with the clamp voltage in the time T4 to T5 (drive period) is supplied to the gate of the NMOS transistor Q100, therefore, in the time T5 to T7 (commutation period), the commutation loss becomes large due to the increase of the ON resistance of the NMOS transistor Q100 and the actually maintained large current together.